THW Client Intern/Co-op - Undergrad (Winter 2025)

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging.

We’re a technology company that leads with our humanity driving our business priorities alongside meaningful social, community, and societal impact.

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THW Client Intern / Co-Op - Undergraduate

Ciena Corporation is a global networking leader holding the #1 market position in our field. The R&D headquarters in Ottawa is home to our world leading Digital Signal Processing (DSP) WaveLogic ASIC chipsets, forming the core of Ciena’s Optical Communications Systems.

We are looking for a passionate and enthusiastic student to work alongside experienced ASIC engineers responsible for design, verification and FPGA prototyping activities of Ciena’s flagship Wavelogic™ optical modems.

This team designs, develops and tests standard protocol framing and mapping IP. During your coop term you will learn about many aspects of the digital ASIC development such as our System Verilog design and verification environments, prototype development, and development automation.

The Opportunity

4 OR 8 month co-op beginning January, 2025.

In this role, you will :

• Work with a fast-paced team developing large scale DSP ASICs for optical communications in the latest ASIC technologies.
• Work with teammates who design using System Verilog, verify using UVM for simulation, run formal verification, synthesis, as well as early lab prototyping
• Interact daily with other developers and team leads for guidance and support

You will gain

• First-hand exposure to real world class ASIC developments using the latest ASIC technologies
• Experience using various tools, method, languages used in ASIC development
• A deeper understanding of ASIC and Hardware techniques
• A strong sense of responsibility for quality and completion of assigned tasks
• Understanding of industry standards and protocols used for telecommunications

The Must Haves :

• Good academic standing in a bachelor’s degree program in Electrical Engineering or Computer Engineering
• Excellent communications skills and the ability to work independently in a highly collaborative team environment
• Programming experience (ideally using at least one of Java, Python, or System Verilog, optionally with Object-Oriented Programming language)
• Familiarity with Linux based development environments

Assets :

• Strong analytical and debugging skills
• Previous experience ASIC or FPGA development programs
• General knowledge of Object-Oriented Programming, or more specifically knowledge of Python and / or Verilog / SystemVerilog programming languages are good foundations
• Experience using Jenkins
• Familiarity with Agile JIRA, Confluence, GIT

Compensation and Benefits (Students)

The pay range for this position is $24.50-$33.00 / hour

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business.

Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.

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At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard.

Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.