Analog Designer 2

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world.

Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded.

Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges.

We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance THE ROLE : The I / O Pad Ring Team is looking for a candidate to perform I / O pad ring physical verification duties and methodology improvements on multiple exciting AMD products being created today.

I / O Pad Ring refers to the input / output interfaces that are loosely found in a ring around the chip. Interfaces like PLL, DDR, GDDR, USB, HDMI, PCIE, GPIO all reside in the IO Pad Ring.

SOC level verification takes many days now. The IO Pad Ring function takes a subset of analog IPs to pre-verify them in order to pre-fetch any issues prior to final integration.

THE PERSON : The candidate should have very good problem solving / debug skills and be able to see through the latter stages of a product delivery.

Strong communication skills will also be required for this role. Day to day responsibilities include, assembly of macros / IPs / RDL into an I / O pad ring database, and then running various verification tools on that assembled database to determine integration issues.

If issues are discovered, communication with various IP owners may be required to facilitate issue resolution. Some of these include DRC, LVS, ERC and Latch up / ESD.

This team is essential to the success of AMD as a cutting edge company. You will be working on some of the most exciting projects the industry has to offer.

CPU / GPU / APU and semi-custom AMD's products featured in Sony PlayStation and Microsoft Xbox, to name a few. It is a very exciting environment and you will be working with the very best in our technology.

KEY RESPONSIBILITIES : Construction of product I / O pad rings using established flows and scripts. Generated views include : Verilog, Def, Spice, and GDSII.

Physical verification on designs that contain up to 200M devices including : LVS, DRC, ERC and PERC. Delivery of all needed waivers(ERC / DRC / EDRC / PERC) and documentation to SoC teams Facilitate ESD and design reviews for 3rd party IPs and I / O ring Tracking of IP versions, visual inspections and in-context XOR verifications.

PREFFED EXPERIENCE : Strong understanding of physical verification checks (LVS / DRC / ERC / PERC), and ability to debug and resolve issues.

Knowledge of chip level integration and ESD / LUP concepts. Must have ability to communicate with various teams to articulate issues, requirements as they pertain to layout in order to facilitate solutions Physical verification experience using Mentor Calibre (LVS, DRC, PERC), and Synopsys tools (ICC / ICC2 / ICV).

Experience doing physical verification for tile of chip physical design would be an asset. Perl programming, TCL, SVRF, TVF programming not required, but would be advantages IP layout design experience and exposure to Cadence is a plus.

Must be able to work independently and as part of a team EDUCATION : Electrical / Computer / Biomedical / Mechanical Engineering Degree and / or Electronics related Diploma LOCATION : Markham, Canada #HYBRID #LI-CC2 Benefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE : The I / O Pad Ring Team is looking for a candidate to perform I / O pad ring physical verification duties and methodology improvements on multiple exciting AMD products being created today.

I / O Pad Ring refers to the input / output interfaces that are loosely found in a ring around the chip. Interfaces like PLL, DDR, GDDR, USB, HDMI, PCIE, GPIO all reside in the IO Pad Ring.

SOC level verification takes many days now. The IO Pad Ring function takes a subset of analog IPs to pre-verify them in order to pre-fetch any issues prior to final integration.

THE PERSON : The candidate should have very good problem solving / debug skills and be able to see through the latter stages of a product delivery.

Strong communication skills will also be required for this role. Day to day responsibilities include, assembly of macros / IPs / RDL into an I / O pad ring database, and then running various verification tools on that assembled database to determine integration issues.

If issues are discovered, communication with various IP owners may be required to facilitate issue resolution. Some of these include DRC, LVS, ERC and Latch up / ESD.

This team is essential to the success of AMD as a cutting edge company. You will be working on some of the most exciting projects the industry has to offer.

CPU / GPU / APU and semi-custom AMD's products featured in Sony PlayStation and Microsoft Xbox, to name a few. It is a very exciting environment and you will be working with the very best in our technology.

KEY RESPONSIBILITIES : Construction of product I / O pad rings using established flows and scripts. Generated views include : Verilog, Def, Spice, and GDSII.

Physical verification on designs that contain up to 200M devices including : LVS, DRC, ERC and PERC. Delivery of all needed waivers(ERC / DRC / EDRC / PERC) and documentation to SoC teams Facilitate ESD and design reviews for 3rd party IPs and I / O ring Tracking of IP versions, visual inspections and in-context XOR verifications.

PREFFED EXPERIENCE : Strong understanding of physical verification checks (LVS / DRC / ERC / PERC), and ability to debug and resolve issues.

Knowledge of chip level integration and ESD / LUP concepts. Must have ability to communicate with various teams to articulate issues, requirements as they pertain to layout in order to facilitate solutions Physical verification experience using Mentor Calibre (LVS, DRC, PERC), and Synopsys tools (ICC / ICC2 / ICV).

Experience doing physical verification for tile of chip physical design would be an asset. Perl programming, TCL, SVRF, TVF programming not required, but would be advantages IP layout design experience and exposure to Cadence is a plus.

Must be able to work independently and as part of a team EDUCATION : Electrical / Computer / Biomedical / Mechanical Engineering Degree and / or Electronics related Diploma LOCATION : Markham, Canada #HYBRID #LI-CC2Benefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.