Job Description : Responsibilities :
Responsibilities :
- Develop / Maintain tests for functional verification with UVM verification at the subsystem level.
- Build testbench components to support the next generation IP.
- Maintain or improve current test libraries to support IP level testing.
- Technically lead IPs in Control Fabric.
- Have exposure to AXI protocol and Bootcode Verification.
- Provide technical support to other teams.
Experience :
- Good at C / C++.
- Good at SV and UVM.
- Good scripting knowledge in Perl, Ruby and Makefile.
- Familiarity with System Verilog and modern verification libraries like UVM.
Academic Credentials :
- Bachelors or Masters degree in computer engineering / Electrical Engineering.
- 5+ years' experience required.
- Top 2 priority skills : C / C++ code and SV and UVM.
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